There is no admission that the background art disclosed in this section legally constitutes prior art.
It is well known that solar cells or photovoltaic cells (PV cells) can be used to convert solar energy into current and voltage, or electric energy. Typical photovoltaic cells include a substrate and two ohmic contacts (i.e., electrode layers) for passing current to an external electrical circuit. The cell also includes an active semiconductor junction, usually comprised of two or three semiconductor layers in series. The two-layer type of semiconductor cell consists of an n-type layer and a p-type layer. The three-layer type includes an intrinsic (i-type) layer positioned between the n-type layer and the p-type layer for absorption of light radiation. The photovoltaic cells operate by having readily excitable electrons that can be energized by solar energy to higher energy levels, thereby creating positively charged holes and negatively charged electrons at the interface of various semiconductor layers. The creation of these positive and negative charge carriers creates a net voltage across the two electrode layers in the photovoltaic cell, and establishes a current of electricity.
In order to improve the performance of photovoltaic cells, it is advantageous to decrease the thickness of the various protective and active layers to reduce materials usage and weight, improve mechanical flexibility, and improve light transmissibility into and through the structure. Thin-layer and ultra-thin-layer photovoltaic cells utilize thin-layer semiconductor materials to form the various active layers of the cells. These thin layer semiconductor materials offer several distinct advantages over thicker crystalline materials, insofar as they can be easily and economically fabricated into a variety of devices by mass production processes.
As the thickness of the various functional layers decreases, the impact of defects within the layer structures and at the layer junction interfaces becomes more pronounced. One such defect is the presence of current-shunting, short circuit defects. These defects seriously impair the performance of the photovoltaic devices fabricated from thin layer semiconductor materials and also detrimentally affect production yield. These process-related defects are thought to either be present in the morphology of the substrate electrode, or develop during the deposition or subsequent processing of the semiconductor layers.
Shunt defects are present in photovoltaic devices when one or more low resistance current paths develop through the semiconductor body of the device, allowing current to pass unimpeded between the electrodes thereof. Under operating conditions, a photovoltaic device in which a shunt defect has developed, exhibits either (1) a low power output, since electrical current collected at the electrodes flows through the defect region (the path of least resistance) in preference to an external load, or (2) complete failure where sufficient current is shunted through the defect region to “short out” the device.
In certain instances, barrier layers may provide passivation of shunt defects. U.S. Pat. No. 4,251,286 to Barnett shows PV cells having n- and p-layers made from copper sulfide and cadmium sulfide forming a heterojunction interface. In one embodiment, the PV cells may include a blocking layer (16) of zinc sulfide formed between the collector p-layer (12) and the back contact (14). In another embodiment, the blocking layer may be a localized cadmium sulfate layer (17) disposed on the exposed portions of the cadmium sulfide active layer.
U.S. Pat. No. 4,598,306 to Nath et al. shows barrier layers formed from oxides, nitrides and carbides of indium, tin, cadmium, zinc, antimony, silicon, and chromium. These barrier layers are transparent and preferably applied between a transparent electrode and the semiconductor body. Such barrier layers were applied to amorphous silicon p-i-n-PV cells having a stainless steel back contact.
U.S. Pat. No. 7,098,058 to Karpov et al. discloses a method of applying a bonding material onto a semiconductor layer having electrical non-uniformities. The formed semiconductor layers of a photovoltaic cell are immersed into a solution of the bonding material and an electrolyte. The semiconductor layers are energized by way of light energy causing an electrical potential within the semiconductor layers. The bonding material is carried to the semiconductor surface by an electrochemical reaction that causes a redistribution of the positive and negative ions of an electrolyte solution. The bonding material becomes selectively applied to areas of aberrant electric potential by way of the energized semiconductor layers.
Electronic transport across a junction of two materials, one of which is a semiconductor, is governed by the alignment of the band structure and the chemical potential of the two materials. Proper alignment results in a good ohmic contact across the junction, while misalignment can result in a potential barrier that must be overcome for the transport of electrons to occur. For semiconductor devices, good ohmic contacts are important to minimize losses in the device and/or across the junction. The degradation of the junction can be a result of chemical instability that may be accelerated by thermal heating from the ambient environment and/or internal device heating, the latter of which may be caused by the loss of energy required to overcome the potential barrier formed at the non-ohmic contact.
A common material for thin layer PV devices is p-type cadmium telluride (CdTe) because it has a bandgap ideally suited for solar absorption and energy conversion. Traditionally, the work function of the metal contact is matched to the semiconducting layer such that no potential barrier exists, allowing the charges to flow freely. However, p-CdTe has a high work function, which limits the materials that can be used to make a back contact with it. Most metals have a lower work function than CdTe and, as a result, will form a Schottky junction between the metal and CdTe layers. This decreases the energy conversion efficiency of the CdTe devices.
To avoid this problem, many researchers and CdTe panel manufacturers apply copper (Cu) to the CdTe layer to form a CuxTe layer that can be contacted by metals such as gold, aluminum, and chromium. Ohmic contacts have been formed using graphite pastes and inks in combination with the copper layers. Single wall carbon nanotube (SWNT) layers have been used previously as a back contact for CdTe devices. However, Cu is always utilized to form a CuxTe layer. The application of copper is often preceded by an etching of the CdTe to produce a Te-rich layer to form CuxTe. A tellurium-rich layer may also be formed at the back contact as a result of a preceding process, such as a negative photoresist step or another step used to passivate pin-holes.
Unfortunately, Cu has the potential to degrade the performance of the CdTe device. Studies have shown that Cu can diffuse through the CdTe at the grain boundaries at moderate temperatures, under illumination, when excess Cu is applied. Cu throughout the CdTe layer can result in a lower shunt resistance, which can lead to a decreased fill factor and lower energy conversion efficiency. Furthermore, Cu can diffuse completely through the CdTe layer and to the p/n-junction into the window layer (typically formed from CdS) of the device. In addition to the problems that arise from Cu in the CdTe layer, when Cu reaches and diffuses into the CdS layer, the VOC may decrease, thereby reducing the energy conversion efficiency even further.
In addition to applying barrier layers to prevent or slow Cu migration, eliminating Cu contact materials altogether have been attempted. One substitute for Cu is to use high work function metal oxides (such as MoO3) to contact the CdTe layer. A thin layer of MoOx/nickel (Ni) has been used to make a back contact to a CdTe device and has resulted in PV properties that are similar to a standard CdTe device with Cu/Ni. The MoOx/Ni finished device was also able to withstand 19 hours of thermal and illumination stress with minimal degradation. However, the non-stoichiometric MoOx layer is an insulator and, thus, the thickness needs to be well controlled to achieve the ohmic contact with the CdTe but avoid the additional series resistance of a thicker layer.
Thus, it would be desirable to provide a buffer or barrier layer that is compatible with CdS/CdTe flexible, thin layer PV cells that is effective for CdTe layers of about 0.5 microns or less and convenient to apply. It would be further desirable to provide a structure and method for an ohmic contact to a semiconducting layer for use in a semiconducting device, such as a photovoltaic solar cell, that avoids the use of Cu in direct contact with a semiconductor layer that is sensitive to Cu absorption and migration, as well as the other issues mentioned above.